// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  aic_top_soc_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  AIC_TOP_WRAPPER
// Version       :  V110
// Date          :  2013/3/10
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  AIC_TOP_WRAPPER 2018/03/20 21:30:01 Create file
// ******************************************************************************

#ifndef __AIC_TOP_SOC_REG_REG_OFFSET_FIELD_H__
#define __AIC_TOP_SOC_REG_REG_OFFSET_FIELD_H__

#define AIC_TOP_SOC_REG_TSENSOR_HIGH_LEN    10
#define AIC_TOP_SOC_REG_TSENSOR_HIGH_OFFSET 16
#define AIC_TOP_SOC_REG_TSENSOR_LOW_LEN     10
#define AIC_TOP_SOC_REG_TSENSOR_LOW_OFFSET  0

#define AIC_TOP_SOC_REG_TSENSOR_SAMPLE_SHIFT_NUM_LEN    4
#define AIC_TOP_SOC_REG_TSENSOR_SAMPLE_SHIFT_NUM_OFFSET 0

#define AIC_TOP_SOC_REG_TSENSOR_TEMP_CT_SEL_LEN    2
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_CT_SEL_OFFSET 12
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_CALIB_LEN     1
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_CALIB_OFFSET  1
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_EN_LEN        1
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_EN_OFFSET     0

#define AIC_TOP_SOC_REG_TSENSOR_ULTRAOVER_LEN    1
#define AIC_TOP_SOC_REG_TSENSOR_ULTRAOVER_OFFSET 2
#define AIC_TOP_SOC_REG_TSENSOR_OVER_LEN         1
#define AIC_TOP_SOC_REG_TSENSOR_OVER_OFFSET      1
#define AIC_TOP_SOC_REG_TSENSOR_UNDER_LEN        1
#define AIC_TOP_SOC_REG_TSENSOR_UNDER_OFFSET     0

#define AIC_TOP_SOC_REG_TSENSOR_ULTRAOVER_INT_MASK_LEN    1
#define AIC_TOP_SOC_REG_TSENSOR_ULTRAOVER_INT_MASK_OFFSET 2
#define AIC_TOP_SOC_REG_TSENSOR_OVER_INT_MASK_LEN         1
#define AIC_TOP_SOC_REG_TSENSOR_OVER_INT_MASK_OFFSET      1
#define AIC_TOP_SOC_REG_TSENSOR_UNDER_INT_MASK_LEN        1
#define AIC_TOP_SOC_REG_TSENSOR_UNDER_INT_MASK_OFFSET     0

#define AIC_TOP_SOC_REG_TSENSOR_TEMP_READY_LEN    1
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_READY_OFFSET 12
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_OUT_LEN      10
#define AIC_TOP_SOC_REG_TSENSOR_TEMP_OUT_OFFSET   0

#define AIC_TOP_SOC_REG_TSENSOR_VALID_LEN     1
#define AIC_TOP_SOC_REG_TSENSOR_VALID_OFFSET  31
#define AIC_TOP_SOC_REG_TSENSOR_SAMPLE_LEN    10
#define AIC_TOP_SOC_REG_TSENSOR_SAMPLE_OFFSET 0

#define AIC_TOP_SOC_REG_TSENSOR_ULTRAOVER_INT_STATUS_LEN    1
#define AIC_TOP_SOC_REG_TSENSOR_ULTRAOVER_INT_STATUS_OFFSET 2
#define AIC_TOP_SOC_REG_TSENSOR_OVER_INT_STATUS_LEN         1
#define AIC_TOP_SOC_REG_TSENSOR_OVER_INT_STATUS_OFFSET      1
#define AIC_TOP_SOC_REG_TSENSOR_UNDER_INT_STATUS_LEN        1
#define AIC_TOP_SOC_REG_TSENSOR_UNDER_INT_STATUS_OFFSET     0

#define AIC_TOP_SOC_REG_TSENSOR_ULTRAHIGH_LEN    10
#define AIC_TOP_SOC_REG_TSENSOR_ULTRAHIGH_OFFSET 0

#define AIC_TOP_SOC_REG_HPM_EN_LEN     1
#define AIC_TOP_SOC_REG_HPM_EN_OFFSET  6
#define AIC_TOP_SOC_REG_HPM_DIV_LEN    6
#define AIC_TOP_SOC_REG_HPM_DIV_OFFSET 0

#define AIC_TOP_SOC_REG_HPM_PC_ORG_1_LEN    10
#define AIC_TOP_SOC_REG_HPM_PC_ORG_1_OFFSET 15
#define AIC_TOP_SOC_REG_HPM_PC_ORG_0_LEN    10
#define AIC_TOP_SOC_REG_HPM_PC_ORG_0_OFFSET 3
#define AIC_TOP_SOC_REG_HPM_PC_VALID_LEN    1
#define AIC_TOP_SOC_REG_HPM_PC_VALID_OFFSET 0

#define AIC_TOP_SOC_REG_CPM_FLAG_DISABLE_LEN    1
#define AIC_TOP_SOC_REG_CPM_FLAG_DISABLE_OFFSET 0

#define AIC_TOP_SOC_REG_CPM_TEST_IN_LEN            4
#define AIC_TOP_SOC_REG_CPM_TEST_IN_OFFSET         16
#define AIC_TOP_SOC_REG_CPM_PULSE_WIDTH_SEL_LEN    1
#define AIC_TOP_SOC_REG_CPM_PULSE_WIDTH_SEL_OFFSET 9
#define AIC_TOP_SOC_REG_CPM_DATA_LIMIT_E_LEN       1
#define AIC_TOP_SOC_REG_CPM_DATA_LIMIT_E_OFFSET    8
#define AIC_TOP_SOC_REG_CMP_DATA_MOD_LEN           2
#define AIC_TOP_SOC_REG_CMP_DATA_MOD_OFFSET        6
#define AIC_TOP_SOC_REG_CPM_PERIOD_LEN             1
#define AIC_TOP_SOC_REG_CPM_PERIOD_OFFSET          5
#define AIC_TOP_SOC_REG_CPM_THRESHOLD_LEN          5
#define AIC_TOP_SOC_REG_CPM_THRESHOLD_OFFSET       0

#define AIC_TOP_SOC_REG_SVT_LL_LEN    4
#define AIC_TOP_SOC_REG_SVT_LL_OFFSET 12
#define AIC_TOP_SOC_REG_SVT_SL_LEN    4
#define AIC_TOP_SOC_REG_SVT_SL_OFFSET 8
#define AIC_TOP_SOC_REG_LVT_LL_LEN    4
#define AIC_TOP_SOC_REG_LVT_LL_OFFSET 4
#define AIC_TOP_SOC_REG_LVT_SL_LEN    4
#define AIC_TOP_SOC_REG_LVT_SL_OFFSET 0

#define AIC_TOP_SOC_REG_CPM_TEST_OUT_LEN    4
#define AIC_TOP_SOC_REG_CPM_TEST_OUT_OFFSET 16
#define AIC_TOP_SOC_REG_CPM_DATA_LEN        6
#define AIC_TOP_SOC_REG_CPM_DATA_OFFSET     0

#define AIC_TOP_SOC_REG_SRST_REQ_LOCAL_HW_AIC_LEN    1
#define AIC_TOP_SOC_REG_SRST_REQ_LOCAL_HW_AIC_OFFSET 0

#define AIC_TOP_SOC_REG_ICG_EN_MBIST_LEN         1
#define AIC_TOP_SOC_REG_ICG_EN_MBIST_OFFSET      2
#define AIC_TOP_SOC_REG_ICG_EN_AIC_LEN           1
#define AIC_TOP_SOC_REG_ICG_EN_AIC_OFFSET        1
#define AIC_TOP_SOC_REG_ICG_EN_SMMU_TRANS_LEN    1
#define AIC_TOP_SOC_REG_ICG_EN_SMMU_TRANS_OFFSET 0

#define AIC_TOP_SOC_REG_AIC_TOP_SOC_SC_RESERVED_REG0_LEN    32
#define AIC_TOP_SOC_REG_AIC_TOP_SOC_SC_RESERVED_REG0_OFFSET 0

#define AIC_TOP_SOC_REG_AIC_TOP_SOC_SC_RESERVED_REG1_LEN    32
#define AIC_TOP_SOC_REG_AIC_TOP_SOC_SC_RESERVED_REG1_OFFSET 0

#endif // __AIC_TOP_SOC_REG_REG_OFFSET_FIELD_H__
